I've had a large collection of BF998 dual gate MOSFETs sitting around in the junkbox for quite a while now (acquired from KE6F), but I've never really known what to do with them. I feel like I own a fairly decent library of QRP/homebrewing literature, but there seems to be very little detailed information on the theory of operation of the dual gate MOSFET. Most of sparse circuit information on the device seems to assume that you already know the basic theory behind it.
I decided that the best way to learn more about the workings of the dual gate MOSFET was to start building circuits and taking measurements. This post is intended to be the first in a series where I will examine different aspects of dual gate MOSFET circuits.
I started by consulting the BF998 Datasheet, as well as additional documentation provided by the manufacturer, NXP. I decided to base my first circuit off of the recommended biasing in the NXP documentation. Below is the schematic for the first setup that I used to examine the bias characteristics of the BF998. A constant voltage (VAGC) was applied to G2 for this test. The datasheet recommended a nominal AGC voltage of 9 V, so I tried to get a voltage on G2 somewhere near that value. I applied a variable bias voltage (VBIAS) to G1 and measured the voltage drops across R6 and R7 in order to calculate the currents in each resistor. The difference in the currents in R6 and R7 indicated the drain current (ID).
|0 V||2.19 V||9.94 V||0 uA|
|2 V||2.43 V||9.70 V||890 uA|
|4 V||3.97 V||8.15 V||6.60 mA|
|5 V||4.78 V||7.35 V||9.58 mA|
|6 V||5.60 V||6.53 V||12.62 mA|
|8 V||7.20 V||4.92 V||18.54 mA|
This data gives us a starting point to see the effect of VG1 on ID. One feature to note about this biasing scheme is the voltage divider bias applied to the source. The literature states that this is used to bring the source to a higher potential than would be possible using a simple low-value source resistor. The rationale for this is to allow the AGC voltage on G2 to be able to swing lower than the source voltage, which will give a much wider AGC range than a biasing scheme with a single source resistor. (This negative voltage in relation to the source is necessary because the BF998 is a depletion-mode FET, similar to your common N-channel JFET. If you look at the datasheet, you see that the pinchoff voltage is negative). I'll touch on this a bit more shortly.
What is interesting is how this biasing scheme differs from the one encountered in most of the QRP literature. Next, I tried to duplicate the biasing scheme scheme used in the W7ZOI 50 MHz preamp. However, I was unsuccessful in getting any significant amount of drain current with G1 grounded (not nearly the amount that W7ZOI was reporting, even when using the same source resistor values that he reported). I could get much more drain current to flow when I applied bias voltage to G1 as I did in the previous experiment. This puzzled me, so I decided to set it aside for now.
A bit more searching on the net lead me to a circuit in another radio; the Electroluminescent Receiver. Dual gate MOSFETs are used liberally in this radio. It turns out the dual gate MOSFET circuit in this receiver derives its lineage from a QRP classic; the Progressive Communication Receiver (ARRL members only). The unique bit about the amplifiers in these receivers is the use of a diode or LED in the source leg to provide biasing. The forward voltage of the diode(s) or LED(s) raises up the source voltage to allow that AGC swing that was mentioned earlier. This is an alternate (and I believe a simpler) way to do the same thing as the voltage divider biasing used previously.
Armed with this information, I changed the biasing to try a LED in the source leg. A green LED was used, since they have a forward voltage of approximately 2 V. I tried two different values of R6, and as before I applied various bias voltages to G1 to see the effects on drain current.
|0 V||0 V||0 uA|
|2 V||512 mV||1.55 mA|
|3 V||1.25 V||3.79 mA|
|4 V||2.03 V||6.15 mA|
|5 V||2.82 V||8.55 mA|
|6 V||3.63 V||11.00 mA|
|7 V||4.42 V||13.39 mA|
|8 V||5.21 V||15.79 mA|
|9 V||5.70 V||17.27 mA|
|10 V||5.83 V||17.67 mA|
These results seem pretty good, although it looks like I was running into the limit of increasing the drain current somewhere around 9 to 10 volts. I suspect that's because the voltage on G1 was approaching the voltage on G2. However, I may be wrong about that, so feel free to correct me.
Next, I decreaed the source resistor to 100 Ω, a value commonly seen in other dual gate MOSFET amplifiers.
|0 V||0 V||0 uA|
|2 V||355 mV||3.55 mA|
|3 V||912 mV||9.12 mA|
|4 V||1.52 V||15.2 mA|
|5 V||2.15 V||21.5 mA|
|6 V||2.79 V||27.9 mA|
Since the maximum drain current for the device is listed as 30 mA, I stopped at 6 V of bias on G1. A bit of tweaking of the bias voltage showed me that I could get a drain current of 10 mA with a G1 voltage of 3.16 V. Since the manufacturer documentation lists a nominal drain current of 10 mA, I decided to stick with this value for now. When it comes time to test IMD, I may want to change this a bit, but for now it's a good starting place.
The plan is now to use the LED biasing scheme when I start investigating the RF characteristics of the device. I suspect a bit more tweaking will be done, but I feel that I have a better grasp of the basic biasing of the circuit. I may look at taking the G1 bias off of the top of D1, or I might use a voltage divider...that's still to be decided by future experiments.