CC-Series, Design, Homebrewing, QRP, Test and Measurement

Dual Gate MOSFET Investigations – Intermodulation

You may have seen in my previous post that I have been working on the latest (and hopefully final) major revision of the CC1. Many of the previous decisions on the radio architecture have been thrown out, perhaps most importantly the decision to use a dual-gate MOSFET as the mixer. In the quest for a replacement, I considered using the old standby, a diode ring mixer, but I wanted to be open to other possibilities as well. As shown in that last post, the KISS mixer from Chris Trask seems to have excellent intermod performance with relative simplicity. So the current plan is to try to build an IF chain using the KISS mixer and see if it will work well in the CC1.

Having quantified the performance of the KISS mixer, the current quest is to find an IF amplifier that will provide decent performance at a reasonable current “price”. With an IIP3 of approximately +30 dBm (I believe it should be able to get the mixer there with some improvements in components), the limiting factor for IP3 performance in the IF chain will be the IF amplifiers. Consider that my current goals for the CC1 receiver are:

  • Dynamic range of around 100 dB
  • Decent sensitivity (less than -130 dB MDS in 400 Hz bandwidth)
  • Reasonable current consumption for portable use (< 60 mA)

In order to achieve this, I’ve determined (using the excellent Cascade08 program from W7ZOI’s LADPAC software suite) that the IF amp that I choose will need the following characteristics:

  • OIP3 of at least +20 dBm (although higher is better since the amp is the limiting factor)
  • modest gain

The current candidate for the IF topology is similar to the design seen in Figure 6.89 in Experimental Methods in RF Design, with no gain until after the first IF filter. To that end, I’ve been looking a various amplifier designs to see if I could find something that would fit (or at least come close to) the requirements above. Bipolar amps are nice, but use a lot of current. MMICs were another possibility; the ones I have found do have about +20 dBm OIP3, but with around 20 mA of current draw and approximately 20 dB of gain, which means the IIP3 is not that great. I figured it wouldn’t hurt to take a look at the dual-gate MOSFET again, as I know that at least they can use modest current and many have excellent noise figure.

Without getting into the weeds of every detail of the experiment that I tried, I’ll just recap the important parts. Initially I used a BF998 with an L-network on gate 1 to transform the 2.2 kΩ input impedance of the amplifier to 50 Ω. A pot was provided to provide variable voltage bias to gate 2. Different permutations of source resistor and gate 2 bias were tried, and the best IIP3 I could get from that amplifier was about -3 dBm (with perhaps 14 dB of gain). OK, but not great. So I decided to give the BF991 a try and see what I could get out of it. Again, I tried many variations of source resistor and gate 2 bias, and was able to find a configuration that is somewhat promising.


You can see in the schematic above that I settled on a source resistor of 100 Ω and “dipped” the gate 2 pot for best IP3, which came out at 5.6 V of bias. I also found in previous trials that leaving the source bypass capacitor out improved the IP3 a few dB and decreased the gain a few dB, which was a worthy improvement. Input and output was matched for 50 Ω. The current consumption was only 4 mA, which is pretty great for an IF amp in a portable radio.


Here is the capture of the OIP3 measurement from my DSA815-TG. Only 10 dB of gain, but that is OK as we wanted modest gain. The IIP3 measured +8 dBm, and when you add in the 10 dB of gain, the OIP3 is +18 dBm, which is pretty close to my original spec, and all for only 4 mA.

This all looks very reasonable. But there’s one problem. The good IP3 is highly dependent on VDD and VG2, especially the gate 2 voltage. As this is going to be a production radio, there needs to be a reliable way to set VG2 during calibration, every time. Also it appears that I probably need some way to keep VDD stable over a variety of voltage inputs, such as a LDO voltage regulator (maybe 9 or 10 V would work). But I need as much headway as possible in VDD in order to get the most out of my dual-gate MOSFET amp. In my experience, they don’t like being voltage-starved. There also appears to be a bit of dependency on the tuning of the input L-network, although that is not as pronounced as the other effects.

As it stands now, this is a promising candidate for the IF amp, but I’ll have to find a way to reduce these dependencies quite a bit in order for it to be viable for a commercial product. That’s my next line of inquiry, and I’ll be sure to have a follow-up post if I am able to get around the remaining limitations

CC-Series, Design, Homebrewing, QRP, Test and Measurement

Single-Ended Mixers and Reverse Isolation

Progress on CC-Series development proceeds at a reasonably-good clip right now. One of my last big hardware bugs to stamp out is some nasty microphonics that seem to be generated by the combination product detector/BFO. Today, I believe that I made some significant progress towards solving it and wanted to share what I learned.

IF Amp & Product Detector from CC-20 Beta 1

I’ve done a lot of reading in Experimental Methods in RF Design (EMRFD) about microphonics in DC receivers (read chapter 8!), and the number one cause of it is poor LO-RF port isolation in the mixer. The CC-Series uses a venerable old circuit which hasn’t seen much use in a while. A dual-gate MOSFET is pressed into double-duty as a product detector and BFO (see above). Since the dual-gate MOSFET product detector is in a single-ended configuration, it inherently has bad LO-RF isolation. This allows VFO (or BFO in this case) signal to leak out the product detector input, and have a good portion of that signal reflect back into the product detector. So naturally, the CC-20 could be experiencing the microphonics because of this phenomena. One of the solutions mentioned in EMRFD is to put an amp in front of the mixer which has excellent reverse isolation (signals coming into the amp output don’t tend to get out of the input, and therefore can’t reflect back in again).

I had the suspicion that the common-source JFET amp in front of the product detector might be the culprit. So what’s the best type of amp to place in front of a single-ended mixer? The common-gate JFET amp is a good and popular choice. However, VE7BPO notes on a recently published web page that the best commonly found amp configuration for this particular parameter appears to be the cascode (see the bottom of the page).

In order to test this theory, I went to work on a project that I had set aside earier: a direct conversion receiver based on the CC-Series product detector. When there was no preamp in front of it, the microphonics were unbearable. I figured that a good way to test my theory would be to put a cascode amp in front of this mixer and see how much it helped. I decided to put a dual-gate MOSFET preamp in front of it, as this is essentially a cascode amp and it fits with the dual-gate MOSFET product detector. Once the new preamp was added, the change was dramatic. The microphonics were gone.

Next, I decided to be a bit more rigorous in my study and quantify the exact difference between the common-source JFET amp and the dual-gate MOSFET amp. First I breadboarded the common-source JFET amp and ran it through the test procedure in the page linked above (at 18 MHz). The results were atrocious. Only 30 dB of reverse isolation, which is worse than the worst amp listed there (the feedback amp). Next, I dug out an old dual-gate MOSFET amp I had breadboarded for my 2008 investigations and ran it through the same test. As expected, the results were vastly superior: 68 dB of reverse isolation. This lines up nicely with Todd’s measured results of >64 dB for the hybrid cascode (I used a spectrum analyzer while he used an oscilloscope, so I was able to get a pretty good measurement down to low signal levels).

So this appears to be strong evidence that the IF amp is the problem. It seems certain that the next version of the CC-Series is going to scrap those awful common-source amps for a much nicer dual-gate MOSFET amp. The lesson to take away from this is that if you are going to use a single-ended mixer for any but the most simplistic applications, it must be fronted with an amplifier with an excellent reverse isolation. While the typical common-gate JFET amp will work OK, for best results it looks like a cascode or dual-gate MOSFET amp is the way to go.

Design, Homebrewing

Dual Gate MOSFET Investigations – Return Loss

Even though a homebrew return loss bridge is a relatively simple piece of gear to build, I’ve never gotten around to building one until now. Which is truly a shame, and something I don’t really have an excuse for, except perhaps laziness. I’m excited to add this essential gear to my stable of test equipment, as I know that I’m going to get a ton of useful data from it in the future. Now that I have all of the necessary equipment for measuring the return loss of the evolving dual gate MOSFET amplifier, it was time to get the job done.

Return Loss Bridge

Test Equipment

  • Power Meter: M3 Electronix FPM-1
  • Voltmeter: Fluke 8840A
  • Signal Generator: Tektronix SG503
  • Return Loss Bridge: Homebrew (51 Ω, ¼ W resistors, FT37-43 bifilar transformer)

The Circuit

Based on the suggestions made on the EMRFD list, I modified the amplifier to incorporate the best practices that were recommended. First off, I tossed out the 100 kΩ gate 2 resistor, which was serving no useful purpose (except for dumping noise into the amp, according to W7ZOI). The bypass cap leads were clipped very short and soldered directly to gate 2. I’ll probably change this to a 10 nF or 1 nF cap in later iterations, but I took the lazy way out and left it as is for now. The other change was the addition of R2, the swamping resistor for the drain inductor. VAGC was set for 9 V, a point which should give nearly the full amplifier gain.

Dual Gate MOSFET Return Loss


Before taking the return loss measurements, I checked out the biasing and gain of the new amplifier configuration. Not surprisingly, the transducer gain dropped to 17.3 dB (-30 dBm input signal at 28.1 MHz), which of course was the whole point of adding R2. The drain current at this bias point is only about 2.5 mA, so there’s still lots of headroom in this amp.

Using the procedure outlined in EMRFD, I measured the amplifier input and output return loss. The SG503 was set to 28.1 MHz with a -10 dBm output level and connected the the RF port of the return loss bridge (RLB). The detector port of the RLB was connected to the FPM-1 and a reading of detector power was made with an open circuit on the unknown port of the RLB. Next, I terminated the output of the amplifier in 50 Ω, connected the unknown port of the RLB to the input of the amp, and applied DC power to the amplifier. The difference between the two readings was the measured input return loss (S11), which was 10.0 dB in this case. Using a handy chart, I translated this into a VSWR of approximately 1.93. Given what I’ve seen in the literature about the poor input return loss characteristics of dual gate MOSFET amplifiers, I was actually pretty pleased with this number.

I repeated the measurement, but this time I terminated the input in 50 Ω and connected the unknown port of the RLB to the amplifier output. This indicated the output return loss (S22) to be 11.9 dB, which is a VSWR of approximately 1.68. This shows that the load transformer is doing a fairly decent job of handling the impedance transformation on the output.

This was a simple test, but the results were satisfying. In the current state, this amplifer should work fine if integrated into a large system, such as a receiver. The real question is the effect that the 2.2 kΩ termination on gate 1 has on noise figure. Speaking of noise figure, I plan to make this measurement next, but I have quite a bit of work to do first. In order to characterize the ENR of my noise generators, I’m going to need to get my hands on a true-RMS detector. I’ll probably end up building the one that Sabin describes in his paper on the EMRFD CD that deals with measuring receiver sensitivity and noise. But that means waiting, since I have to order a few of the parts. I’ve also got more reading to do in order to better understand everything that’s going on with noise figure measurements. I also need to start thinking about how I’m going to get my hands on a spectrum analyzer to make IMD measurements. Which is funny because I work on very nice spectrum analzyers every day at work!


Dual Gate MOSFET Revelations from W7ZOI

Some days I feel like I can’t see the forest for the trees. After submitting my last dual gate MOSFET experiment to the EMRFD group for review, I got a nice note from Henning suggesting that I needed to bypass gate 2 directly. Of course, like a three-year old who has to constantly ask “Why?”, I questioned how necessary it was to get the bypass capacitor right at gate 2. Wes, W7ZOI kindly gave me an education on the pitfalls of an unbypassed gate 2:

Yes, it can make a profound difference. The capacitor really need
to be right at the gate. If you don’t bypass gate 2, you will dump
the noise voltage from the resistor driving gate 2 right into the
FET. With 100K, that voltage will be high. This could really trash
the amplifier NF performance, turning a stellar performer into
something that is pretty bad for NF. But use a really good bypass
cap that is going to do a good job at VHF and UHF. A 1000 pF with
really short leads is good. This is a good place to use a chip cap
even if you are among the folks who don’t like SMT parts.

Many thanks to Wes for putting up with such a stupid question. One thing that I really appreciate about his writing is that he can explain things to you in a way that make it seem completely obvious, yet without talking down to you. He also goes on to explain the rationale behind two commonly seen resistors in dual gate MOSFET amps:

There are two resistors that we often see in the drain circuits.
One is a swamping resistor that is directly across the primary (drain
winding) of the output transformer. This merely constrains the gain
to a smaller value. It also serves to provide a clean output R.
This loading R will help to stabilize the amplifier, but will not do
a lot at UHF.

This is an area worthy of further investigation. Specfially how much it degrades IMD and NF compared to the benefits

The other resistor is one that is right in series with the drain.
This is often in the region of 20 to 100 Ohms. This serves to
provide a wideband load that kills UHF oscillations. The utility of
this resistor can be studied with a microwave stability analysis,
easily done with numerous programs, or from scratch if you are
willing to do some analysis. You will see examples of the small
drain R in some of the amplifiers in emrfd.

This looks like a good project for LTSpice. I figured that looking into these MOSFETs would be pretty straightforward once I understood the biasing, but this investigation is leading into all kinds of interesting side roads. I can tell that I have my work cut out for me!

Design, Homebrewing

Dual Gate MOSFET Investigations – Gain and AGC

Having determined some basic characteristics of the biasing of the BF998 dual gate MOSFET in a previous experiment, it was now time to look into the gain and AGC performance of the amplifier. A few changes were made to the original circuit to turn it into a proper RF amplifier.

Test Equipment

  • Power Meter: M3 Electronix FPM-1
  • Voltmeter: Fluke 8840A
  • Signal Generator: Tektronix SG503

Initial Test Conditions

The gate 1 voltage (VBIAS) was initially biased to 3.16 V, a level that was previously determined to give about 10 mA of drain current when gate 2 is biased to 9.2 V. The input signal was set to a frequency of approximately 28.1 MHz, to give an idea of the amplifier performance in the upper HF bands. The output power of the signal generator was set to -30.0 dBm into a 50 Ω resistive load. This gave me enough power to make a good measurement with the FPM-1 while avoiding the problem of gain compression. All gain measurements are based off of this amplifier input power (in other words, the amplifier gain described in this report is the transducer gain).

The Circuit

The DC biasing of the circuit is virtually identical to the final configuration determined in the first experiment. However, there have been some changes in regard to the input and output circuitry. First of all, the gate 1 bias is now fed through a 2.2 kΩ resistor which is bypassed to AC ground with a 100 nF capacitor. This sets the input impedance to 2.2 kΩ. Values around 2 kΩ seem to be fairly common in the literature, apparently because of the noise figure benefits. I would like to investigate this further in a later experiment, but for now we’ll go with the wisdom of others. A typical L-network was placed on the input to transform the 50 Ω amplifier input impedance to the 2.2 kΩ impedance that gate 1 wants to see. The drain inductor was replaced with a 10:2 ratio transformer to give the drain a load of 1.25 kΩ to work into when a 50 Ω load is placed on the amplifier output. Again, this is another area where I decided to go with the wisdom of others. This drain load values seems reasonable based on other FET amplifiers I’ve used, but it might also be an area worth investigating later.

Dual Gate MOSFET Gain


Under the initial conditions described above, I measured an output power of -6.1 dBm, which indicates a transducer gain of 23.9 dB. This seems like a reasonable and believeable amount of gain from a single amplifier given the biasing levels established. I decided to vary VBIAS a bit to determine the point of maximum gain for the amplifier. At a gate 1 voltage of 3.43 V, I measured -5.9 dBm of output power, or a gain of 24.1 dB. There is a slight amount of difference between the two voltages, but not enough to be significant. It seems that the initial estimate worked fairly well.

AGC Characteristics

Next, the circuit was modified slightly to examine the AGC characteristics of the BF998. Both the source and gate 1 were biased to approximately 3 V using a blue LED. This biasing method is very convenient, simple, and stable, even if it may not bias gate 1 to its ideal point. This reduced the drain current to 6.6 mA, which would mean a slightly lower maximum gain, but also would be a more power-efficient way to run the amp. I could have used two red or green diodes in series, or a string of small-signal diodes as seen in the Hybrid Cascode amplifier, but the blue LED uses the least parts (and is pretty to boot). The fixed voltage divider bias was removed from gate 2, and in its place a variable AGC voltage (VAGC) was applied. The same -30.0 dBm input power was used, and the output power was measured at different settings of VAGC.



As you can see in the table and chart below, there is a large AGC voltage range with very little gain variation, then a sharp knee where there is a steep slope of gain reduction. The knee occurs at an AGC voltage of about 3 V. Between 2 V and 3 V is the largest gain variation (about 40 dB). This AGC response curve actually appears to agree fairly well with the curve published in the Philips RF Manual 3rd Edition Appendix for the BF998. The AGC range of approximately 50 dB also seems in line with the data published by NXP. It does look plausible that two of these amplifiers cascaded together could provide nearly 100 dB of gain reduction (another experiment idea for later).

2 V -55.7 dBm -25.7 dB
2.25 V -52.8 dBm -22.8 dB
2.5 V -37.2 dBm -7.2 dB
2.75 V -23.3 dBm 6.7 dB
3 V -16.0 dBm 14.0 dB
4 V -12.6 dBm 17.4 dB
5 V -11.2 dBm 18.8 dB
6 V -10.4 dBm 19.6 dB
7 V -9.9 dBm 20.1 dB
8 V -9.5 dBm 20.5 dB
9 V -9.1 dBm 20.9 dB
10 V -9.0 dBm 21.0 dB

Dual Gate MOSFET AGC Graph

Next, I intend to build a return loss bridge (finally!) and get some measurements on this amplifier. I also need to look into what it will take to measure noise figure, and get started on that test rig as well.