I’ve been absent from the blog for a while because I’ve been knee-deep in developing the prototype for the first radio kit for my as-of-yet-unnamed open source kitbiz. The design makes extensive use of JFETs in cascode configuration. JFET cascode amps and mixers are very solid performers, but the issue of widely varying Idss in JFETs was giving me cause for concern in regard to how repeatable the design would be for mass production. In order to set my mind at ease, I did some research on the most stable way to bias JFETs for Id and did a quick experiment to confirm what I was reading.
The most common form of JFET biasing that you seem to find in homebrew QRP projects is self-biasing; where a resistor is placed between the source and ground, and the gate is tied to DC ground. This is a convenient way to bias a N-channel FET when using a single-polarity voltage supply, but it’s definitely not the most stable form of biasing. According to Application Note 102 from Siliconix, using a constant current source to bias the FET will ensure a constant Id, but that seems like a bit of overkill in a simple QRP rig.
The image above shows the transfer characteristic curves for a 2N4339 biased with four different methods: constant voltage, constant current, self-bias, and combo-bias. The two Id-Vgs curves in each graph represent the normal production range of Idss. As you can see in graph (c), the load line QA-QB has a fair amount of slope, which indicates that Id will vary quite a bit as Idss varies. Graph (a) shows constant voltage bias, which provides the worst variation of Id by far. The source resistor provides the slope of the load line, so increasing Rs will flatten the slope and reduce the Id variation, but the problem is that it also chokes off Id and reduces the amplifier transconductance.
Combo-biasing (presented in graph (d)) helps to flatten the slope without losing all of your drain current. The load line in the self-bias graph has an intercept at the origin, which represents the gate at a DC voltage of 0 V. If you leave the source resistor in, and apply a positive voltage on the gate, the load line slope will flatten as seen in graph (d).
In order to see this effect for myself, I conducted a quick experiment with a batch of ten J211s that I picked from random from a bag of parts procured from Mouser. The first thing that I did was measure Idss by configuring the circuit on the left below and measuring the current through the source. Next, to measure the self-bias configuration, I placed a source resistor of 1 kΩ in the circuit and again measured the drain current. Finally, the combo-bias configuration was tested by applying 2.9 V to the gate through a 100 kΩ resistor, for a target drain current of 4 mA (the procedure for choosing the proper gate voltage is detailed in the application note).
[table id=1 /]
As you can see in the table above, self-biasing controls the drain current to a smaller range than Idss, but if you compare the standard deviation to the sample mean, you can see that it’s roughly the same. The values of drain current in the self-bias circuit are roughly proportional to Idss. On the other hand, in the combo-bias circuit it’s obvious that the drain currents are even more tightly controlled even though the mean is about double what it is in the self-bias circuit. The standard deviation as a percentage of the mean is approximately half of the self-bias circuit.
Note: it has been a while since I’ve taken Statistics, so I believe that I’ve made a valid comparison, but if I haven’t I’m sure someone will let me know.
Now I understand one of the reasons that the string of source diodes is used in the Hycas IF amplifier. This provides the gate with a few volts of bias, which gives combo-biasing and drain current stability. The Siliconix application note shows voltage divider bias as a way of achieving this, but I’ve always been a fan of using diode bias where possible. This method of biasing should provide a good way of controlling for manufacturing variations when using JFETs in bulk.