Si5351A Investigations Part 7

Here's the post I know that a lot of you have been waiting for. Buzz around the Si5351 has been picking up at a pretty rapid clip over the last month or so, but a lot of homebrewers have been hesitant to use it in their designs because one critical parameter has not yet been measured: phase noise.

Phase noise measurements seem to be one of the least easily accessible to the typical ham homebrewer, but fortunately for us, we have in our ranks some engineers with access to excellent T&M gear that most of us would never be able to afford for our home workbench. Thomas LA3PNA was able to put me in touch with one such engineer, John Miles KE5FX. I don't know much about John, but I should, as it looks like he has developed the TimePod phase noise measurement device and the TimeLab analysis software (which is very slick, I must say).

John was generous enough to make a variety of phase noise measurements on the Si5351A Breakout Board that I sent him. Below, I present some plots of the phase noise measurement that were taken at various frequencies and under a few different conditions.

Before I get to a brief commentary, here are the plots. The first two plots were taken at 3 MHz, first with 2 mA output current then at 8 mA output current. Then you will find 10 MHz, 13.371 MHz (in both fractional and integer divider modes), 14 MHz, 100 MHz, and then a composite plot of all of the different traces.

3_MHz_2_mA 3_MHz_8_mA 10_MHz_powerup_default overlay_frac_int_mode_13mhz 14_MHz_CLK0_with_CLK1_at_0 100_MHz_CLK1_PLL_auto_calc_8mA overlay

I believe that the plots speak for themselves fairly well. If you compare these results to the receivers in the Sherwood Engineering receiver table, I think you'll see that the Si5351 acquits itself quite nicely for such an inexpensive part. Personally, I think the Si5351 is eminently usable for many receiver applications, except perhaps the most high-performance. Certainly for the price, it's going to be extremely hard to beat. I hope this motivates those sitting on the fence to decide if the Si5351 will meet their needs.

Finally, I would like to share a new video of the Si5351 in action, courtesy of prolific builder Pete N6QW. Here's Pete having the very first QSO with his new SSB QRP rig built using one of the Adafruit Si5351A Breakout Boards:

I would like to sincerely thank KE5FX for taking the time to make these measurements for the community and for allowing me to share them with you. If you have any ideas for critical phase noise measurements that aren't included here, let me know in the comments and perhaps we can get those made as well.

Edit: I failed to mention that these measurements were taken with a plain old 25 MHz ECS crystal as the reference oscillator. With a higher-quality reference oscillator, one would expect even better phase noise performance.

18 thoughts on “Si5351A Investigations Part 7”

  1. Good work everyone!
    I think we'll be hearing a lot more about this chip. Combined with cheap microcontroller boards and a vast 'erector set' of code libraries, anyone can now make high performance tuning systems without having to wrestle with the voodoo of analog oscillators.

  2. All those test frequencies are pretty much even numbers. Would a choice of truly random frequencies give different results? This part has lots of advantages over the Si570. Two outputs can operate at the same freq in quadrature, for example, ideal for the softrock guys. Cheap. Less power. I'd put up with a little bit of extra noise if necessary.

  3. Jerry, that's a good point, but there is a 13.371 MHz measurement in there as well and it looks similar to the other HF plots.

    There is a phase register in the Si5351, but it's only 7 bits so I have some doubt that it has the requisite resolution to give good phase accuracy across a wide frequency range. At the very least, one could use the old trick to use FFs to derive a /4 quadrature clock.

    I agree the slightly more noise (but it's still quite decent) is a good trade off for the price.

  4. Could be fine, I haven't fully figured it out. But the posting says "13.371 MHz (in both fractional and integer divider modes)". Suggests to me there's some small integer ratio out there to get from 25 MHz to 13.371 Mhz. If you get to using all 20 bits of the b and c values in the Si5351's a+b/c fractional divider, then updates to the PLL will occur far less frequently. With subsequently greater noise. I think. Anyways, I hope the Si5351 works out. And I really like your reversible double mixer scheme for an SSB xcvr.

  5. > If you get to using all 20 bits of the b and c values in the Si5351's a+b/c
    > fractional divider, then updates to the PLL will occur far less frequently.

    More likely the updates are frequent enough but not quite as accurate.

  6. After reviewing the datasheet a further, I'm becoming convinced the Si5351 is well worth looking at. Convinced I should buy one and start playing with it. See my post at,16 Will continue the conversation there.
    Jason, you're right that the 7 bit phase shift won't work well for a quadrature clock in the general case. At frequencies below 5 MHz there isn't enough range in those 7 bits to do a 90 deg phase shift. At higher frequencies you would need to choose your VCO freq carefully to get sufficient accuracy on the phase shift, as it occurs in steps of 1/(4*VCOFreq). I believe most SDR code can correct for small errors in phasing. So I think it could be made to work well enough on 40 through 10 meters.

  7. Jerry,

    I will ask KE5FX if he can make a few more phase noise measurements that we can be sure are using a fractional PLL divider ratio and then update the post when I have the results. Thanks for the suggestions!


  8. Since I'm not totally sure what a worst case of (a+(b/c)) is, I'd suggest just ticking up one Hz at a time. Let us know if you are using a fractional output divider, SiLabs thinks you're better off with integer output dividers and only the PLL loopback divider fractional when necessary. Ideally, include a register dump of some sort with each plot so we can better figure out any weirdness that pops up.

  9. The Si5338 draws more power, is in a more difficult package, and at $10 is 10x the price. But if nothing else, rev 1.4 of the datasheet gives significant clues about what's going on in the Si5351. The final entry of table 12 on page 14 shows that a fractional output divider does not add all that much jitter over integer mode. The description of the MultiSynth fractional divider on page 19 explains why.
    In a previous posting, I encouraged you to use integer mode VFO. But since in the proposed Si5351 transceiver the VFO and BFO are at unrelated frequencies, one or the other must be fractional mode. Might as well make the BFO integer mode, as it mostly stays put.

  10. Scratch the last paragraph in my previous posting, my head was in the Si5338 which has one VCO. The Si5351 has two VCO's, so BFO and VFO could both have integer mode output dividers if you choose.

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